This invention relates generally to a semiconductor device and to the production thereof. More particularly, this invention relates to technology that is effective when applied to a semiconductor device having a DRAM (Dynamic Random Access Memory).
Memory cells of a DRAM are generally arranged at points of intersection between a plurality of word lines and a plurality of bit lines that are arranged in the form of a matrix on a main plane of a semiconductor substrate. Each memory cell comprises one MISFET (Metal Insulator Semiconductor Field Effect Transistor) for selecting the memory cell and one information storage capacitance device (capacitor) connected in series with this MISFET.
The MISFET for selecting the memory cell is formed in an active region encompassed by a device isolation region, and comprises mainly a gate oxide film, a gate electrode formed integrally with a word line and a pair of semiconductor regions constituting a source and a drain. Generally, two of such MISFETs are formed in one active region, and one of the source/drain (semiconductor regions) of these two MISFETs is shared at the center of the active region. The bit line is disposed over the MISFET and is connected electrically to the semiconductor region thus shared. The capacitor is disposed likewise over the MISFET and is connected electrically to the other source/drain.
Japanese Patent Laid-open No. 7084/1995, for example, discloses a DRAM having a Capacitor-Over-Bit-line (COB) structure formed by disposing the capacitors over the bit lines. The DRAM described in this reference employs a structure in which a lower electrode (accumulation electrode) of each capacitor arranged over the bit line is processed into a cylindrical shape, and a capacitance insulating film and an upper electrode (plate electrode) are formed on this lower electrode. Being shaped into a cylindrical shape, the surface of the lower electrode can be increased so as to supplement the decrease of the storage charge quantity (Cs) of the capacitor resulting from miniaturization of the memory cell. In the memory cell having such a COB structure, cubing of the capacitor structure to a certain extent is essentially necessary in order to secure the desired operation reliability as a semiconductor memory device.
It is anticipated, however, that even the cubing of the capacitor structure will not be sufficient to secure the necessary capacitance value (storage charge quantity) in the latest semiconductor devices that are highly integrated, particularly in those which have a capacity of 256 Mbit (megabit) or more.
The journal xe2x80x9cApplied Physicsxe2x80x9d, Vol. 65, No. 11, pp. 1111-1112, published by the Society of Applied Physics, Nov. 10, 1996, examines the possibility of the use of high dielectric materials (ferroelectric materials), such as tantalum oxide (Ta2O5) or STO (SrTO3) or BST (BaxSr1xe2x88x92xTO3), for the insulating film of the capacitor. Ta2O5 has a specific inductive capacity of as high as about 20, and STO and BST have an extremely high specific inductive capacity of about 200 to about 500. Therefore, if these high dielectric constant films are used, a higher capacitance value could be acquired more easily than the silicon oxide film and the silicon nitride film that have been used in the past. STO and BST, in particular, have a high dielectric constant, and are therefore expected to exhibit a remarkable effect of increasing the capacitance value.
Film formation of STO and BST is conducted in an oxidizing atmosphere. Therefore, when the silicon materials that have been used in the past are used for the capacitor electrode, a silicon oxide film having a low dielectric constant is formed undesirably on the electrode interface. For this reason, the possible use of Ru (ruthenium), Pt (platinum), RuO2 (ruthenium oxide), etc, having a high oxidation resistance has been examined as the electrode material for the capacitor.
However, the inventors of this invention have confirmed that the following problems arise when precious metals, such as Ru, Pt, etc, or their suicides or oxides, are used for the electrode materials, particularly for the upper electrode. The problems that will be explained below are not particularly known in the art, but have been discovered as a result of experiments conducted by the present inventors. Incidentally, the term xe2x80x9cprecious metalxe2x80x9d as used in this specification refers to gold (Au), silver (Ag) and platinum group metals (ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) and platinum (Pt)).
The first problem is that when a precious metal is used for the upper electrode, the electric connection between a contact portion (through-hole plug) with the upper layer wire and the upper electrode becomes unstable, or a connection defect arises.
The first cause of this problem is oxygen contained in the precious metal that forms the upper electrode. A CVD process is employed when the film of the precious metal such as Ru or Pt is formed. Since the starting gas contains oxygen in this CVD process, the resulting precious metal film contains oxygen, too. Also, the re is the case where the film constituent elements contain oxygen from the beginning such as in the case of RuO2. To open a through-hole for the connection to the upper electrode in an inter-layer insulating film covering the upper electrode, a photoresist film is used generally. However, when this photoresist film is removed by ashing, the upper electrode (film made of the precious metal) below the through-hole absorbs oxygen in the ashing atmosphere. When heat-treatment is conducted after the through-hole plug is formed, oxygen in the film reacts with the metal constituting the plug and forms a metal oxide. The plug comprises generally a barrier metal such as titanium nitride and a main conductor layer such as tungsten. In this case, titanium in the barrier metal reacts with oxygen and forms titanium oxide having a high resistivity. Since such titanium oxide is formed structurally between the upper electrode and the plug, the electric contact between the upper electrode and the plug is impeded, so that the problem of unstableness (drop of connection reliability) of the electric connection described above occurs.
The second cause is that an etching selection ratio cannot be balanced substantially between the precious metal constituting the upper electrode and a silicon oxide film serving as the inter-layer insulating film that covers the upper electrode. The through-hole for the connection to the upper electrode is formed when the opening is bored in the silicon oxide film serving as the inter-layer-insulating film. Dry etching of the silicon oxide film is generally conducted using a photoresist film as a mask to bore this opening. In this instance, since the etching selection ratio cannot be balanced sufficiently between the silicon oxide film and the precious metal constituting the lower electrode, the through-hole is formed in such a fashion as to penetrate through the upper electrode. Since the through-hole is so formed as to penetrate through the upper electrode in this way, the contact and the area between the plu upper electrode inside the through-hole becomes small and the problem of the drop of connection reliability develops. It may be possible to control the etching time so that etching can be completed on the surface of the upper electrode, but this method is difficult in actual practice for the following reasons. The supply of power to the upper electrode is provided from its upper layer wire through the through-hole plug. However, the supply of power or the connection of the wire from the upper layer wire is made also to the wire (first layer wire) that is formed in the same wire layer as the bit lines. In other words, two or more kinds of through-holes, that is, the through-hole for the plug for the connection to the upper electrode and the through-hole for the plug for the connection to the first layer wire, exist. Since the bit line (first layer wire) is formed below the capacitor, the depth of the through-hole for the connection to the upper electrode is smaller than the depth of the through-hole for the connection to the first layer wire. When the separate process steps are conducted to form these two kinds of through-holes, the number of the process steps increases. It is therefore unavoidably necessary to process them simultaneously. Consequently, when etching is stopped on the surface of the upper electrode, the through-hole reaching the first layer wire cannot be formed. When the through-hole reaching the first layer wire is bored, on the contrary, the through-hole must be formed unavoidably in such a fashion as to penetrate through the upper electrode as long as the etching selection ratio cannot be secured for the upper electrode.
When the through-hole is so formed as to penetrate through the upper electrode, and particularly when the upper electrode is made of a material that evaporates in the oxidizing atmosphere (such as Ru or RuOx), the upper electrode below the through-hole is etched in the step (ashing step) of removing the photoresist film after the through-hole processing (etching), and is recessed in some cases from the section of the through-hole. In this case, even when the plug is formed after the formation of the through-hole, normal contact cannot be established because the material of the lower electrode is recessed from the through-hole section, inviting a connection defect. The problem of the evaporation of the lower electrode material due to ashing or the problem of etching occurs also when the through-hole does not penetrate through the lower electrode, but is more critical than when it penetrates through the lower electrode.
The second problem is that the resistance value of the upper electrode cannot be lowered when a precious metal is used for the upper electrode. Fluctuation of the upper electrode potential (reference potential) occurs under the transient state at the time of read-out of the memory cell. Unless the resistance value of the upper electrode is lowered, the influences of such a transient fluctuation are great. In consequence, the possibility of a read error exists. From the aspect of cut-off of the external noise, too, the resistance value of the upper electrode is preferably small.
The reason why such a problem occurs is because the film thickness of the precious metal cannot be increased. The precious metals have a large internal stress (compressive stress), and if the film thickness is increased, degradation of the capacitor characteristics occurs due to the influences of the stress.
It is an object of the invention to provide a semiconductor integrated circuit device that has a high connection reliability between a capacitor upper electrode and a plug connected to an upper layer wire, and is free from the occurrence of a connection defect.
It is another object of the invention to provide a semiconductor integrated circuit device that can reduce the resistance of the capacitance upper electrode.
These and other objects and novel features of the invention will become more apparent from the following description in this specification when taken in connection with the accompanying drawings.
The outline of typical features embodiments described in this application will be briefly described as follows.
According to one aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film) and in which a wire (second layer wire) on the capacitor and the second electrode are connected by a connection member (through-hole plug), wherein the connection member contains a metal which degrades its conductivity upon oxidation, the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the second layer contains oxygen to such an extent that oxygen does not form a metal oxide, or the resulting metal oxide does not impede electric conduction between the second layer and the connection member. Alternatively, the second layer does not contain oxygen.
In such a semiconductor integrated circuit device, the second layer does not contain oxygen, or even when it does, oxygen is contained in such an amount that a metal oxide that impedes electric conduction is hardly formed. In consequence, the material that impedes electric conduction is hot formed between the second layer and the connection member, and the connection reliability between the upper electrode of the capacitor and the through-hole plug can be improved. As a result, the reliability of the semiconductor integrated circuit device can be improved.
Incidentally, the connection member can include a barrier layer made of titanium nitride or an adhesive layer. If the upper electrode coming into contact with the connection member contains oxygen, oxygen reacts with titanium inside the titanium nitride because the connection member contains titanium nitride (TiN), and forms titanium oxide (TiO) that impede electric conduction. In accordance with the present invention, however, the second layer does not contain oxygen or contains it in only a limited amount even when it does. Therefore, titanium oxide (TiO) is not formed, and connection between the connection member and the second layer can be kept satisfactory. In other words, connection between the second electrode and the connection member can be kept satisfactory.
In accordance with the invention, the connection member may be formed in such a fashion as to penetrate through the second electrode. In such a case, too, a good connection can be established at least between the second layer and the connection member even though connection between the first layer and the connection member is not satisfactory. Eventually, connection between the second electrode and the connection member can be kept satisfactory.
According to another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film) and in which a wire (second layer wire) on the capacitor and the second electrode are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the second layer is made of a material having a lower etching rate than that of a material constituting the first layer under the condition where an insulating film is etched.
According to such a semiconductor integrated circuit device, the second layer is allowed to function as an etching stopper during the etching process in which a connection hole (through-hole) is bored in an inter-layer insulating film (silicon oxide film, for example) on the second layer. Consequently, it becomes possible to prevent penetration of the through-hole through the second electrode and to improve the connection reliability between the through-hole plug and the second electrode. The second layer can be formed simultaneously with a connection hole having a greater hole depth (for example, a connection hole connected to a first layer wire formed below the capacitor), and the connection hole formation step can be simplified.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film) and in which a wire (second layer wire) on the capacitor and the second electrode are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the second layer is made of a material having a higher oxidation resistance than a material constituting the first layer, or a material having a smaller evaporation rate in an oxidizing atmosphere.
According to such a semiconductor integrated circuit device, the second layer has a high oxidation resistance or a small evaporation rate in the oxidizing atmosphere. Therefore, damage and evaporation of the second layer can be restricted in the photoresist-removing step (ashing step) after processing of the through-hole. In this case, even when the first layer is made of a material having a low oxidizability or having an evaporation property in the oxidizing atmosphere (ruthenium, for example), the second layer functions as a blocking film in the ashing atmosphere, and etching or evaporation of the first layer can be prevented.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film), and in which a wire (second layer wire) on the capacitor and a second layer are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the second layer is made of a material having a lower resistivity than the material constituting the first layer.
According to such a semiconductor integrated circuit device, the second layer uses a material having a low resistivity. Therefore, the resistance value of the second electrode can be reduced and the performance of the semiconductor integrated circuit device can be improved.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film), and in which a wire (second layer wire) on the capacitor and the second electrode are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the internal stress of the second electrode is lower than the internal stress when the second layer is constituted by the material constituting the first layer.
According to such a semiconductor integrated circuit device, a laminate film of a second layer material (tungsten, for example) and a first layer material that constitutes the second electrode can more greatly reduce the internal stress than when the second electrode is constituted as a whole by the first layer material (ruthenium, for example). The precious metal used as the first layer material has generally a large internal stress, and when the second electrode is constituted by such a precious metal, the capacitor characteristics (such as a leakage current) increase, resulting in a degradation of the refresh performance of the DRAM. This semiconductor integrated circuit device can avoid such a problem because the internal stress can be reduced.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film) and in which a wire (second layer wire) on the capacitor and the second electrode are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the angle between a taper surface and a base in a processing section when the second layer material is processed by anisotropic dry etching is greater than the angle between the taper surface and the base in the processing section of the first layer material under the same etching condition.
In other words, the second electrode material has a higher etchability than the first electrode material. Therefore, the etchability of the second electrode comprising the first and second layers is higher than that of the second electrode made solely of the first layer material.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film) and in which a wire (second layer wire) on the capacitor, and the second electrode are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), the first electrode is shaped into a columnar or cylindrical cubic shape, the film thickness T1 of the first layer satisfies the condition T1 greater than (dxe2x88x922xc3x97Tins)/2, and the film thickness T2 of the second layer satisfies the condition T2 greater than T1, where d is the distance between adjacent first electrodes or a cylindrical inner diameter of the first electrode, and Tins is the film thickness of the capacitance insulating film.
From the condition T1 greater than (dxe2x88x922xc3x97Tins)/2, the first layer must have a film thickness sufficient to bury at least concavo-convexities resulting from the lower electrode (first electrode) and the capacitor insulating film. Since the first layer is generally made of a precious metal such as ruthenium, its film thickness is preferably made as small as possible so long as it can satisfy the condition described above, in order to reduce the internal stress. On the other hand, the film thickness of the second layer is greater than that of the first layer from the condition T2 greater than T1, so as to secure sufficient conductivity and to reduce the stress of the second electrode as a whole.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit device which includes a capacitor comprising a first electrode (lower electrode), a second electrode (upper electrode) and a capacitance insulating film (ferroelectric body or high dielectric film) and in which a wire (second layer wire) on the capacitor and the second electrode are connected by a connection member (through-hole plug), wherein the second electrode includes a first layer (lower layer) and a second layer (upper layer), and the end portions of the first and second layers are processed into a taper shape. This sectional shape can be formed in such a fashion that the distance from the end (leg) of the vertical drawn from the upper end of the taper surface to the surface of the base to the lower end of the taper surface is at least xc2xd of the minimum processing size.
Since the end portions of the first and second layers are thus processed into a taper shape, the reliability of the semiconductor integrated circuit device and its production yield can be improved. The first layer (made of a precious metal such as ruthenium) has lower etchability than the second layer. Therefore, a side film having a low evaporation property (such as ruthenium oxide) is formed on the etching section of the first layer. When the subsequent process step is continued under such a condition where the side film exists, the side film peels off from the etching section and changes to dust in the washing step, and so forth. The dust becomes the factor that undesirably lowers the production yield of the semiconductor integrated circuit device. For this reason, the present invention etches the second electrode into a taper shape lest the side film is formed. This means can restrict the occurrence of dust and can improve the production yield of the semiconductor integrated circuit device and its reliability.
Incidentally, in the semiconductor integrated circuit device described above, the first layer can be a precious metal film, a silicide or oxide film of the precious metals or their compound film. Examples of the first layer include a platinum film, a ruthenium film, a ruthenium silicide film and an SRO (SrRuOx) film. In this instance, the capacitance insulating film may be a BST (BaxSr1xe2x88x92xTiO3) film, an STO (SrTiO3) film or a tantalum oxide (Ta2O5) film.
The first layer can be a titanium nitride film while the capacitance insulating film can be a tantalum oxide (Ta2O5) film.
The second layer can be a metal film of an element belonging to the Groups IVb, Vb and VIb, their nitride film, their silicide film or their compound film. Examples of the second layer is a tungsten (W) film, a titanium (Ti) film, a tantalum (Ta) film, a tungsten nitride (WN) film, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a titanium aluminum nitride (TiAlN) film, a titanium silicon nitride (TiSiN) film, a tungsten silicon nitride (WSIN) film and a tantalum silicon nitride (TaSiN) film. These metal films or metal compound films are superior in oxidation resistance and etching resistance to the material of the first layer, and have a lower resistivity and lower stress. When these materials are used for the second layer, the functions described above can be accomplished.
The second electrode may further include a third layer comprising a titanium nitride film or a titanium compound film such as a titanium silicon nitride film in addition to the first and second layers. The titanium nitride film has the function of absorbing hydrogen and can exhibit the function as a hydrogen barrier after the capacitor is formed. The metal oxide material is used for the capacitor insulating film, as described above, and the diffusion of hydrogen is not preferable. When the titanium nitride film is formed in this way, the performance of the capaci tor insulating film can be kept at a high level.
The first electrode can comprise a film of precious metals or their silicide or oxide film, or their compound film. Examples include a platinum film, a ruthenium film, a ruthenium silicide film and an SRO (SrRuOx) film.
The semiconductor integrated circuit device includes a local wire in the same layer as the second electrode. This local wire is formed by the same process step as the second electrode. Since the second electrode, the resistance of which is lowered by using the second layer, is used for the wire, the second electrodes (plate electrodes) between the memory mats, for example, can be connected to one another without using an upper layer wire. As a consequence, the number of through-holes extending to the upper layer wires can be reduced, the freedom of layout can be improved and a higher integration density of the semiconductor integrated circuit device can be accomplished.
A method of producing a semiconductor integrated circuit device according to the invention comprises the step of forming bit lines and first layer wires on a MISFET on a main plane of a semiconductor substrate through a first inter-layer insulating film, forming a second inter-layer insulating film and an electrode-forming insulating film, and boring holes in the electrode-forming insulating film; forming a metal or a metal compound for burying the inside of the holes, removing the electrode-forming insulating film or forming a metal film or a metal compound film covering the inner wall of the holes, and forming a columnar or cylindrical first electrode; depositing a ferroelectric or high dielectric capacitance insulating film to cover the first electrode, and depositing further a first conductor layer and a second conductor layer; etching the first and second conductor layers to form a second electrode; and depositing a third inter-layer insulating film covering the second electrode, and forming first connection holes reaching the second electrode and second connection holes reaching the first layer wire by etching; wherein the second layer functions as an etching stopper from the time at which the bottom portion of the first connection holes reaches the second electrode until the time at which the bottom portion of the second connection holes reaches the first layer wire.
In the step of etching the second electrode, the first layer is etched by using the second layer, that is patterned, as a mask after the second layer is etched.
This production method can produce the semiconductor integrated circuit device described above.